The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high density semiconductor devices with submicron design features and active regions isolated by shallow insulated trenches.
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor. The quality and thickness of the gate oxide are crucial to the performance of the finished device.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material (or xe2x80x9ctrench fillxe2x80x9d), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the barrier nitride layer as a polish stop. In subsequent operations, the nitride and pad oxide are stripped off, a thin gate oxide layer is grown on the exposed silicon of the substrate, and a polysilicon layer is deposited on the gate oxide and etched to form gate electodes.
Disadvantageously, the gate oxide layer typically does not grow uniformly. It tends to be thinner at the trench edges, because the gate oxide growth rate is smaller there due to the curvature of the trench edges; that is, the gate oxide grows at a decreased rate at the trench edges because the silicon at the trench edges has a different crystallographic orientation than the main surface of the substrate. The thinness of the gate oxide at the trench edges allows the subsequently deposited polysilicon to overlap the trench edges. This is shown in FIG. 1, illustrating the substrate 1, trench edges 1a, liner oxide 2, insulating material 3, gate oxide 4 and polysilicon 5. The overlap of polysilicon increases the chance of polysilicon remaining in the trench after it is etched to form the gates. This residual polysilicon, along with the thin gate oxide at the trench edges, increases the electric field strength at the trench edges, which can cause a breakdown of the gate oxide, thereby decreasing device reliability.
There exists a continuing need for shallow trench isolation methodology wherein the resulting gate oxide layer at the trench edges exhibits high reliability and prevents the polysilicon layer from overlapping the trench edges.
An object of the present invention is a method of manufacturing a semiconductor device having a shallow trench isolation region and a gate oxide with high integrity.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a method of manufacturing a semiconductor device having an insulated trench formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises: forming a pad oxide layer on a main surface of the substrate or epitaxial layer; forming a barrier nitride layer having an upper surface on the pad oxide layer; providing a mask having an opening on the barrier nitride layer; etching to remove portions of the underlying barrier nitride and pad oxide layers and to form a trench in the substrate or epitaxial layer, which trench has a surface layer comprising side surfaces intersecting the main surface at edges; ion implanting impurities, at an acute angle, into a portion of the side surfaces and a portion of the main surface proximal to the edges for increasing the oxidation rate of the ion implanted portions; forming an oxide liner on the surface layer of the trench, on the edges, and in contact with the pad oxide layer, the oxide liner having a thickness at the edges on the ion implanted portions greater than that of the remainder of the oxide liner; removing the barrier nitride layer and pad oxide layer; and forming a gate oxide layer on the main surface in contact with the oxide liner, the gate oxide layer having a thickness proximal to the edges greater than or equal to that of the remainder of the gate oxide layer.
Another aspect of the present invention is a method of manufacturing a semiconductor device having an insulated trench formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises: forming a pad oxide layer on a main surface of the substrate or epitaxial layer; forming a barrier nitride layer having an upper surface on the pad oxide layer; providing a mask having an opening on the barrier nitride layer; etching to remove portions of the underlying barrier nitride and pad oxide layers and to form a trench in the substrate or epitaxial layer, which trench comprises side surfaces intersecting the main surface at edges; forming an oxide layer lining the surface layer of the trench, on the edges, and in contact with the pad oxide layer; ion implanting impurities at an acute angle through the oxide liner and into a portion of the side surfaces and a portion of the main surface proximal to the edges, thereby increasing the oxidation rate of the ion implanted portions; depositing an insulating material to fill the trench and cover the barrier nitride layer; planarizing such that an upper surface of the insulating material is substantially flush with the upper surface of the barrier nitride layer; removing the barrier nitride layer and the pad oxide layer; and growing a gate oxide layer on the main surface and on the edges, the gate oxide layer having a thickness at the edges which is greater than that of the remainder of the gate oxide layer.
A still further aspect of the present invention is a semiconductor device comprising: a substrate or epitaxial layer formed in the substrate; a trench, formed in the substrate or epitaxial layer, having a surface layer comprising side surfaces intersecting a main surface of the substrate or epitaxial layer at edges, wherein a portion of the side surface and a portion of the main surface proximal to the edges contain impurities; a thermally grown oxide liner on the surface layer of the trench and on the edges, the liner having a thickness proximal to the edges greater than a thickness of the liner at the remainder of the surface layer; an insulating material filling the trench; and a gate oxide layer on the main surface in contact with the oxide liner, the gate oxide layer having a thickness proximal to the edges greater than or equal to a thickness of the gate oxide layer at the remainder of the main surface.
Additional objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.